The present invention relates to a negative voltage level shifter circuit for shifting the voltage level of an input signal to a negative voltage level.
Devices that use voltages different from the voltage of an input signal are exemplified by flash memories (batch erase type memories) and EPROMs (Erasable Programmable Read Only Memories) and the like. In such a device, it is necessary to shift the voltage level of an input signal to a high voltage or negative voltage. Circuits that shift the voltage level of an input signal like this are referred to as level shifter circuits, and among these, circuits which shift a voltage level to a negative voltage are referred to as negative voltage level shifter circuits. In addition, the negative voltage to which a negative voltage level shifter circuit shifts a voltage level is, for example, -8 V, -10 V, -12 V or the like.
A negative voltage level shifter circuit according to the prior art is disclosed in Japanese Patent Laid-Open Publication HEI 9-320282 (FIG. 4). Below described is operation of this negative voltage level shifter circuit with reference to FIG. 4. First, when a signal of a level Vcc is inputted as an input signal "in", a transistor P1 turns off. Further, as a result of level inversion of the input signal "in" by an inverter inv1, a transistor P2 turns on, so that the level of an output signal "out" rises to Vcc. Then, a transistor N1 turns on, causing a transistor N2 to turn off. Therefore, the output signal "out" is fixed to Vcc.
When a signal of a level Vss (e.g., 0 V) is inputted as the input signal "in", the transistor P1 turns on. Further, since the level of the input signal "in" is inverted by the inverter inv1 so that Vcc is outputted, the transistor P2 turns off. Meanwhile, by the transistor P1 turning on, the transistor N2 turns off and the transistor N1 turns off. As a result, the level of the output signal "out" is pulled down to Vneg (e.g., -9 V).
Thus, the level Vcc or Vss of the input signal "in" is shifted to the level Vcc or Vneg and outputted as the output signal "out".
However, the negative voltage level shifter circuit of the prior art described above has the following problems. That is, in the case of this negative voltage level shifter circuit, since the level Vcc or Vss of the input signal "in" is shifted to the level Vcc or Vneg as described above, the transistor N1 turns on when the input signal "in" of the level Vcc is inputted. On this account, the negative voltage Vneg is applied to the drain of the transistor P1 while the power supply voltage Vcc is applied to its source. In this case, the maximum value of the voltage applied to the transistor P1 is -Vneg+Vcc. Given here that Vneg is -9 V and that Vcc is 3 V, then the transistor P1 is required to have a breakdown voltage of 12 V.
The breakdown voltage of a transistor, although depending also on the oxide layer thickness of the transistor, generally decreases as the size of the transistor decreases. Accordingly, along with advances of microstructure and downsizing of memory cells, the array pitch of transistors or the like constituting the decoder decreases so that the transistors are also necessarily downsized resultantly. Therefore, there is a tendency that the breakdown voltage of transistors constituting the decoder decreases with the recent micro-miniaturization of semiconductor storage devices.
Meanwhile, in flash memories, there has been a growing demand for higher programming speed and erasing speed. Below described is the method for enhancing these speeds. FIG. 5 shows a cell structure of a flash memory cell. A flash memory cell comprises a gate portion composed of a control gate 101 and a floating gate 102 with an interlayer insulator 100 interposed therebetween, a source portion 105 and a drain portion 106 located on both sides of the gate portion in a substrate 104 with tunnel oxide 103 interposed therebetween. Below described is the operation of a flash memory (FN--FN type flash memory) that uses the FN (Fowler-Nordheim) tunneling phenomenon for programming operation and erasing operation with memory cells as described above.
For programming, Vneg (e.g., -9 V) is applied to the control gate 101 while Vpd (e.g., 5 V) is applied to the drain portion 106. Then, the FN tunneling phenomenon occurs on the drain side, causing electrons to be pulled out from the floating gate 102, so that the threshold value of the transistor forming the memory cell goes lower, thus information being written therein. For erasing, on the other hand, Vpp (e.g., 12 V) is applied to the control gate 101 while Vneg (e.g., -9 V) is applied to the drain portion 106, the source portion 105 and the substrate 104. Then, the FN tunneling phenomenon occurs in the channel layer, causing electrons to be injected into the floating gate 102, so that the threshold value of the transistor forming the memory cell goes higher, thus information being erased. Applied voltage conditions for each operation of the above-described programming and erasing operations plus reading operation are collectively shown in Table 1:
TABLE 1 ______________________________________ Control Substrate gate 101 Drain 106 Source 105 104 ______________________________________ Programming -9 V 5 V F 0 V Erasing 12 V -9 V -9 V -9 V Reading 3 V 1 V 0 V 0 V ______________________________________ F: Floating state
Also, in the case of a flash memory (ETOX type flash memory) that uses channel hot electrons for programming and erasing operations, for programming, Vpp (e.g., 12 V) is applied to the control gate while Vpd (e.g., 5 V) is applied to the drain. Then, with the source at Vss (e.g., 0 V), a current flows in the channel layer, causing channel hot electrons to be generated around the drain. Further, electrons are injected into the floating gate, so that the threshold value of the transistor forming the memory cell goes higher, thus information being written therein. For erasing, on the other hand, Vneg (e.g., -9 V) is applied to the control gate while Vpd (e.g., 5 V) is applied to the drain. Then, the FN tunneling phenomenon occurs on the drain side, causing electrons to be pulled out from the floating gate, so that the threshold value of the transistor forming the memory cell goes lower, thus information being erased. That is, the operation for erasing is similar to the foregoing programming operation of the FN--FN type flash memory. Applied voltage conditions for each operation of the above-described programming and erasing operations plus reading operation are collectively shown in Table 2:
TABLE 2 ______________________________________ Control Substrate gate 101 Drain 106 Source 105 104 ______________________________________ Programming 12 V 5 V 0 V 0 V Erasing -9 V 5 V F 0 V Reading 3 V 1 V 0 V 0 V ______________________________________ F: Floating state
Here is discussed a method for enhancing the speed of programming characteristics of the FN--FN type flash memory. FIG. 6 shows an example of the programming characteristics of the FN--FN type flash memory, showing a relationship between voltage application time to the control gate 101 and the threshold value of the transistor forming the memory cell (hereinafter, referred to simply as memory cell threshold) in the case where the voltage applied to the control gate 101 is changed to -8 V, -10 V and -12 V. As can be seen from the figure, increasing the absolute value of the negative voltage applied to the control gate 101 allows the programming speed to be enhanced. It is noted that applying a negative voltage to the control gate 101 corresponds to erasing in the case of the ETOX type flash memory. Therefore, for the ETOX type flash memory, the erasing speed can be enhanced by increasing the absolute value of the negative voltage applied to the control gate.
However, as described above, there has been a tendency in recent years that the breakdown voltage lowers, whereas there is an issue that negative voltage level shifters capable of supplying a negative voltage of a high absolute value to the control gate of the memory cell have not yet been provided, which makes it unrealizable to enhance the programming speed of the FN--FN type flash memory or the erasing speed of the ETOX type flash memory. For example, in the conventional negative voltage level shifter shown in FIG. 4, given that the breakdown voltage of its constituent transistors P1, P2, N1 and N2 is 12 V, then
breakdown voltage=-Vneg +Vcc. PA1 first shift means which comprises a latch circuit and an inverter, the latch circuit being made up of two n-MOS transistors and two p-MOS transistors, and which shifts an input signal of the power supply voltage level to the power supply voltage level and shifts an input signal of the reference voltage level to a second negative voltage level; PA1 second shift means which comprises a latch circuit and an inverter, the latch circuit being made up of two n-MOS transistors and two p-MOS transistors, and which shifts the second negative voltage level to the reference voltage level and shifts the reference voltage level to the first negative voltage level; and PA1 an inverter which shifts the power supply voltage level obtained by the first shift means to the second negative voltage level and shifts the second negative voltage level obtained by the first shift means to the reference voltage level and then feeds the resulting voltage level to the second shift means. PA1 first shift means which comprises a latch circuit, an inverter and a p-MOS transistor that inhibits a second negative voltage from being biased forward, the latch circuit being made up of two n-MOS transistors and one p-MOS transistor, and which shifts an input signal of the power supply voltage level to the power supply voltage level and shifts an input signal of the reference voltage level to the second negative voltage level; and PA1 second shift means which comprises a latch circuit, an inverter and a p-MOS transistor that inhibits the second negative voltage from being biased forward, the latch circuit being made up of two n-MOS transistors and one p-MOS transistor, and which shifts the power supply voltage level to the reference voltage level and shifts the second negative voltage level to the first negative voltage level.
Therefore, if the power supply voltage Vcc is 3 V, then ##EQU1## so that only -9 V can be supplied. Consequently, according to FIG. 6, there is an issue that the flash memory, although capable of enhancing the programming speed or the erasing speed by applying a voltage of -12 V to its control gate, is disabled from exerting the capability.
Accordingly, an object of the present invention is to provide a negative voltage level shifter circuit capable of increasing the absolute value of an outputted negative voltage without increasing the breakdown voltage of the constituent transistors, as well as a nonvolatile semiconductor storage device using this negative voltage level shifter circuit.
In order to achieve the aforementioned object, there is provided a negative voltage level shifter circuit for shifting an input signal of either a power supply voltage level or a reference voltage level to either the reference voltage level or a first negative voltage level, comprising:
With this constitution, the second negative voltage level Vnmin is set to an intermediate level between the reference voltage level Vss and the first negative voltage level Vneg, and a level shift is performed in two steps by two shift means having the same constitution via the second negative voltage level Vnmin. Thus, a negative voltage large in absolute value can be obtained by the two shift means having the same circuit construction as the conventional counterpart without using any special circuit construction.
Also, there is provided a negative voltage level shifter circuit for shifting an input signal of either a power supply voltage level or a reference voltage level to either the reference voltage level or a first negative voltage level, comprising:
With this constitution, the second negative voltage level Vnmin is set to an intermediate level between the reference voltage level Vss and the first negative voltage level Vneg, and a level shift is performed in two steps by two shift means having the same constitution via the second negative voltage level Vnmin. Thus, a negative voltage large in absolute value can be obtained without using any special circuit construction.
In one embodiment of the present invention, the second negative voltage is so set as to have an absolute value equal to or smaller than a difference between an absolute value of a breakdown voltage of the transistors constituting the first shift means and an absolute value of the power supply voltage.
With this constitution, even if the breakdown voltage of the transistors constituting the first shift means is a breakdown voltage of ordinary transistors that have conventionally been used, a negative voltage large in absolute value can be obtained by the two-step level shift.
In one embodiment of the present invention, the second negative voltage is obtained by a threshold reduction of at least one of the p-MOS transistors connected in series to each other.
With this constitution, the second negative voltage Vnmin can be obtained at low current consumption and with a simple circuit construction, without using any additional power supply for generation of the second negative voltage.
Also, there is provided a nonvolatile semiconductor storage device comprising the negative voltage level shifter circuit as defined in claim 1.
With this constitution, by using a negative voltage level shifter which, even if made up of transistors having a low breakdown voltage, is capable of obtaining a negative voltage large in absolute value, the nonvolatile semiconductor storage device can be reduced in size and enhanced in programming speed and erasing speed.